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? semiconductor components industries, llc, 2007 july, 2007 - rev. 4 1 publication order number: NB7L86M/d NB7L86M 2.5v/3.3v 12 gb/s differential clock/data smartgate with cml output and internal termination the NB7L86M is a multi-function differential logic gate, which can be configured as an and/nand, or/nor, xor/xnor, or 2:1 mux. this device is part of the gigacomm family of high performance silicon germanium products. the NB7L86M is an ultra-low jitter multi-logic gate with a maximum data rate of 12 gb/s and input clock frequency of 8 ghz suitable for data communication systems, telecom systems, fiber channel, and gige applications. differential inputs incorporate internal 50 termination resistors and accept lvnecl (negative ecl), lvpecl (positive ecl), lvcmos, lvttl, cml, or lvds. the differential 16 ma cml output provides matching internal 50 termination, and 400 mv output swing when externally terminated 50 to v cc . the device is housed in a low profile 3x3 mm 16-pin qfn package. application notes, models, and support documentation are available on www.onsemi.com. features ? maximum input clock frequency up to 8 ghz ? maximum input data rate up to 12 gb/s typical ? < 0.5 ps of rms clock jitter ? < 10 ps of data dependent jitter ? 30 ps typical rise and fall times ? 90 ps typical propagation delay ? 2 ps typical within device skew ? operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? cml output level (400 mv peak-t o-peak output) di fferential output ? 50 internal input and output termination resistors ? functionally compatible with existing 2.5 v/3.3 v lvel, lvep, ep and sg devices ? pb-free packages are available figure 1. simplified logic diagram d0 q sel vtd0 q sel vtd0 50 50 d0 d1 vtd1 vtd1 50 50 d1 50 50 vtsel http://onsemi.com qfn16 mn suffix case 485g marking diagram * *for additional marking information, refer to application note and8002/d. a = assembly location l = wafer lot y = year w = work week = pb-free package 16 nb7l 86m alyw 1 see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information
NB7L86M http://onsemi.com 2 vtd1 d1 d1 vtd1 vtd0 d0 d0 vtd0 v ee q q v cc v cc sel sel vtsel 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB7L86M exposed pad (ep) figure 2. pin configuration (top view) table 1. pin description pin name i/o description 1, 9 v cc power supply positive supply voltage. all v cc pins must be externally connected to power supply to guarantee proper operation. 2 sel lvpecl, cml, lvcmos, lvttl, lvds input inverted differential select logic input. 3 sel lvpecl, cml, lvcmos, lvttl, lvds input non-inverted differential select logic input. 4 v tsel - common internal 50 termination pin for sel/sel . see table 6. (note 1) 5 v td1 - internal 50 termination pin for d1. see table 6. (note 1) 6 d1 lvpecl, cml, lvcmos, lvttl, lvds input non-inverted differential clock/data input d1. (note 1) 7 d1 lvpecl, cml, lvcmos, lvttl, lvds input inverted differential clock/data input d1 . (note 1) 8 v td1 - internal 50 termination pin for d1 . see table 6. (note 1) 10 q cml output non-inverted output with internal 50 source termination resistor. (note 2) 11 q cml output inverted output with internal 50 source termination resistor. (note 2) 12 v ee power supply negative supply voltage. all v ee pins must be externally connected to power supply to guarantee proper operation. 13 v td0 - internal 50 termination pin for d0. (note 1) 14 d0 lvpecl, cml, lvcmos, lvttl, lvds input non-inverted differential clock/data input d0 . (note 1) 15 d0 lvpecl, cml, lvcmos, lvttl, lvds input non-inverted differential clock/data input d0. (note 1) 16 v td0 - internal 50 termination pin for d0 . (note 1) - ep - exposed pad. thermal pad on the package bottom must be attached to a heatsinking conduit to improve heat transfer. it is recommended to connect the ep to the lower potential (v ee ). 1. in the dif ferential configuration when the input termination pins (v tdx , v tdx , v tsel ) are connected to a common termination voltage or left open, and if no signal is applied on dx, dx , sel and sel then the device will be susceptible to self-oscillation. 2. cml output require 50 receiver termination resistor to vcc for proper operation.
NB7L86M http://onsemi.com 3 q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel figure 3. configuration for and/nand function v cc vt or v bb d0 d0 d1 d1 r d v ee v cc table 2. and/nand truth table (note 3) b and b d0 d1 sel q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 3. d0 , d1 , sel are complementary of d0, d1, sel unless specified otherwise. figure 4. configuration for or/nor function table 3. or/nor truth table (note 4) 0 0 1 1 d0 1 1 1 1 d1 0 1 0 1 sel or 0 1 1 1 q q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel v cc vt or v bb d0 d0 d1 d1 4. d0 , d1 , sel are complementary of d0, d1, sel unless specified otherwise. q sel vtd0 q sel vtd0 50 50 vtd1 vtd1 50 50 50 50 vtsel d0 d0 d1 d1 figure 5. configuration for xor/xnor function 1 0 0 d1 0 1 0 1 sel xor 0 1 1 0 q table 4. xor/xnor truth table (note 5) 0 0 1 1 d0 1 5. d0 , d1 , sel are complementary of d0, d1, sel unless specified otherwise.
NB7L86M http://onsemi.com 4 d0 q sel vtd0 q sel vtd0 50 50 d0 d1 vtd1 vtd1 50 50 d1 50 50 vtsel figure 6. configuration for 2:1 mux function d1 d0 q table 5. 2:1 mux truth table (note 6) 1 0 sel 6. d0 , d1 , sel are complementary of d0, d1, sel unless specified otherwise. table 6. attributes characteristics value esd protection human body model machine model charged device model > 1500 v > 50 v > 500 v moisture sensitivity (note 7) pb pkg pb-free pkg qfn-16 level 1 level 1 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 400 meets or exceeds jedec spec eia/jesd78 ic latchup test 7. for additional moisture sensitivity information, refer to application note and8003/d. table 7. maximum ratings symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v i input voltage v ee = 0 v v ee v i v cc 3.6 v v inpp differential input voltage |d - d | v cc - v ee 2.8 v v cc - v ee < 2.8 v 2.8 |v cc - v ee | v v i in input current through r t (50 resistor) continuous surge 25 50 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range qfn-16 -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (note 8) 0 lfpm 500 lfpm qfn-16 qfn-16 42 36 c/w c/w jc thermal resistance (junction-to-case) 2s2p (note 8) qfn-16 3 to 4 c/w t sol wave solder pb pb-free 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 8. jedec standard multilayer board - 2s2p (2 signal, 2 power).
NB7L86M http://onsemi.com 5 table 8. dc characteristics ( v cc = 2.375 v to 3.465 v, v ee = 0 v, t a = -40 c to +85 c) symbol characteristic min typ max unit i cc power supply current (inputs and outputs open) 38 50 ma v oh output high voltage (notes 9 and 10) v cc - 60 v cc - 30 v cc mv v ol output low voltage (notes 9 and 10) v cc - 460 v cc - 400 v cc - 310 mv differential input driven single-ended (see figures 16 & 18) v th input threshold reference voltage range (note 11) 1125 v cc - 75 mv v ih single-ended input high voltage (note 12) v th + 75 v cc mv v il single-ended input low voltage (note 12) v ee v cc - 150 mv differential inputs driven differentially (see figures 17 & 19) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage v ee v cc - 75 mv v cmr input common mode range (differential configuration) 1163 v cc C 38 mv v id differential input voltage (v ihd - v ild ) 75 2500 mv i ih input high current d0/d0 /d1/d1 sel/sel 0 0 50 20 150 150 a i il input low current d0/d0 /d1/d1 sel/sel -50 -50 50 20 100 100 a r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 r temp coef internal i/o termination resistor temperature coefficient 6.38 m / c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed cir cuit board with maintained airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature ran ge. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied ind ividually under normal operating conditions and not valid simultaneously. 9. cml outputs require 50 receiver termination resistors to v cc for proper operation. 10. input and output parameters vary 1:1 with v cc . 11. v th is applied to the complementary input when operating in single-ended mode. 12. v cmr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc .
NB7L86M http://onsemi.com 6 table 9. ac characteristics (v cc = 2.375 v to 3.465 v, v ee = 0 v; note 13) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@v inppmin )f in 4 ghz (see figure 7) f in 8 ghz 240 125 350 230 240 125 350 230 240 125 350 230 mv f data maximum operating data rate 10.7 12 10.7 12 10.7 12 gb/s t plh , t phl propagation delay to dx/dx to q/q output differential @ 1 ghz sel/sel to q/q (see figure 7) 70 110 90 135 120 180 70 110 90 135 120 180 70 110 90 135 120 180 ps t skew duty cycle skew (note 14) device-to-device skew (note 15) 2.0 5.0 10 20 2.0 5.0 10 20 2.0 5.0 10 20 ps t jitter rms random clock jitter (note 16) f in = 4 ghz f in =8 ghz peak/peak data dependent jitter f data = 5 gb/s (note 17) f data =10 gb/s 0.2 0.2 2.0 4.0 0.5 0.5 8.0 10 0.2 0.2 2.0 4.0 0.5 0.5 8.0 10 0.2 0.2 2.0 4.0 0.5 0.5 8.0 10 ps v inpp input voltage swing/sensitivity (differential configuration) (note 18) 75 400 2500 75 400 2500 75 400 2500 mv t r t f output rise/fall times @ 1 ghz q, q (20% - 80%) 35 60 35 60 35 60 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit bo ard with maintained airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature ran ge. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied ind ividually under normal operating conditions and not valid simultaneously. 13. measured by forcing v inpp (typ) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% - 80%). 14. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw- and tpw+ @1 ghz. 15. device to device skew is measured between outputs under identical transition @ 1 ghz. 16. additive rms jitter with 50% duty cycle clock signal. 17. additive peak-to-peak data dependent jitter with input nrz data (prbs 2 ^23 -1). 18. v inpp (max) cannot exceed v cc - v ee . input voltage swing is a single-ended measurement operating in differential mode. input frequency (ghz) figure 7. output voltage amplitude (v outpp ) versus input clock frequency (f in ) at ambient temperature (typical) output voltage amplitude (mv) 500 400 300 200 100 0 12 11 10 9 8 7 6 5 4 3 2 1 0 v cc - v ee = 3.3 v v cc - v ee = 2.5 v
NB7L86M http://onsemi.com 7 figure 8. typical output waveform at 2.488 gb/s with prbs 2 ^23 -1 (v inpp = 75 mv) figure 9. typical output waveform at 2.488 gb/s with prbs 2 ^23 -1 (v inpp = 400 mv) figure 10. typical output waveform at 10 gb/s with prbs 2 ^23 -1 (v inpp = 75 mv) figure 11. typical output waveform at 10 gb/s with prbs 2 ^23 -1 (v inpp = 400 mv) figure 12. typical output waveform at 12 gb/s with prbs 2 ^23 -1 (v inpp = 75 mv) figure 13. typical output waveform at 12 gb/s with prbs 2 ^23 -1 (v inpp = 400 mv) time (72 ps/div) time (72 ps/div) time (20 ps/div) time (20 ps/div) time (16 ps/div) time (16 ps/div) voltage (45 mv/div) voltage (45 mv/div) voltage (45 mv/div) voltage (45 mv/div) voltage (45 mv/div) voltage (45 mv/div) ddj = 1.2 ps* ddj = 1.2 ps* ddj = 2 ps** ddj = 2 ps** ddj = 4 ps*** ddj = 4 ps*** *input signal ddj = 10 ps **input signal ddj = 12 ps ***input signal ddj = 14 ps
NB7L86M http://onsemi.com 8 figure 14. ac reference measurement d d q q t phl t plh v inpp = v ih (d) - v il (d) v outpp = v oh (q) - v ol (q) driver device receiver device qd figure 15. typical termination for output driver and device evaluation (refer to application note and8173 - termination and interface of on semiconductor of ecl logic devices with cml output structure) q d v cc 50 50 z = 50 z = 50 figure 16. differential input driven single-ended figure 17. differential inputs driven differentially figure 18. v th diagram figure 19. v cmr diagram d v cc gnd v ih v ihmin v ihmax v thmax v th v th v thmin v cmmax v cmmax d v cmr v cc gnd d d v th v th d d v ilmax v il v ilmin d v ildmax v ihdmax v id = v ihd - v ild v ildtyp v ihdtyp v ildmin v ihdmin
NB7L86M http://onsemi.com 9 q q v cc 16 ma 50 50 figure 20. cml output structure v ee table 10. interfacing options interfacing options connections cml connect vtd0, vtd0 , vtd1, vtd1 , vtsel to v cc lvds connect vtd0, vtd0 together for d0 input. connect vtd1, vtd1 together for d0 input. leave vtsel open for sel input. ac-coupled bias vtd0, vtd0 , vtsel and vtd1, vtd1 inputs within (v cmr ) common mode range rsecl, lvpecl standard ecl termination techniques. see and8020/d. lvttl, lvcmos an external voltage should be applied to the unused complementary differential input. nominal voltage 1.5 v for lvttl and v cc /2 for lvcmos inputs.
NB7L86M http://onsemi.com 10 application information all inputs can accept pecl, cml, and lvds signal levels. the input voltage can range from v cc to 1.2 v. examples interfaces are illustrated below in a 50 environment (z = 50 ). 50 v cc d d 50 NB7L86M v cc v td v ee v cc q 50 50 NB7L86M v ee figure 21. cml to cml interface z q z figure 22. pecl to cml receiver interface 50 z v cc v cc lvds driver d d 50 NB7L86M v ee v td v ee figure 23. lvds to cml receiver interface 50 z z v cc v cc pecl driver d d 50 NB7L86M v ee v bias v td v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values 50 50 v td v cc v td v bias v td z
NB7L86M http://onsemi.com 11 ordering information device package shipping ? NB7L86Mmn qfn-16 123 units/rail NB7L86Mmng qfn-16 (pb-free) 123 units/rail NB7L86Mmnr2 qfn-16 3000 tape & reel NB7L86Mmnr2g qfn-16 (pb-free) 3000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7L86M http://onsemi.com 12 package dimensions qfn16 3x3, 0.5p mn suffix case 485g-01 issue c mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ?? ?? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NB7L86M/d publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 literature fulfillment : ?literature distribution center for on semiconductor ?p .o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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